Toshiba High Performance Microprocessor Manual De Usuario
Toshiba Develops High Performance Microprocessor
Core
-‘MeP-h1’is the World’s First 1GHz Configurable Processor-
Toshiba Corporation has announced that it has developed a new
high-end processor core, MeP-h1, the first configurable
microprocessor to achieve a 1GHz clock speed. The MeP-h1 is
based on Toshiba’s “Media embedded Processor” (MeP)
architecture for digital consumer and other high performance
SoCs. It gives designers the flexibility to customize processors at
the design stage, including the ability to change processor
configurations and add custom instructions to satisfy application
requirements.
The performance of the new core was boosted by increasing the
number of instruction execution pipeline stages to nine, from five in
Toshiba’s previous processor core. The new core is also optimized
for design of high-performance customized processors by
integration of a reorder buffer circuit that manages and shortens
waiting cycles for user extension instructions. The present
implementation of the core was manufactured with 65nanometer
(nm) process technology, and that too contributed to achieving the
1GHz clock speed. The new configurable processor core is
designed with register transfer level description (RTL) and can be
manufactured with other process technology, including 90nm
technology.
Development background:
The market for digital equipment supporting images, audio and
communications is growing fast. However, the required
performance and type of data processing in system LSI differs by
application, and the overall volume of handled data is rapidly
increasing. As a result, there is growing demand for customizable
high-end processor core, MeP-h1, the first configurable
microprocessor to achieve a 1GHz clock speed. The MeP-h1 is
based on Toshiba’s “Media embedded Processor” (MeP)
architecture for digital consumer and other high performance
SoCs. It gives designers the flexibility to customize processors at
the design stage, including the ability to change processor
configurations and add custom instructions to satisfy application
requirements.
The performance of the new core was boosted by increasing the
number of instruction execution pipeline stages to nine, from five in
Toshiba’s previous processor core. The new core is also optimized
for design of high-performance customized processors by
integration of a reorder buffer circuit that manages and shortens
waiting cycles for user extension instructions. The present
implementation of the core was manufactured with 65nanometer
(nm) process technology, and that too contributed to achieving the
1GHz clock speed. The new configurable processor core is
designed with register transfer level description (RTL) and can be
manufactured with other process technology, including 90nm
technology.
Development background:
The market for digital equipment supporting images, audio and
communications is growing fast. However, the required
performance and type of data processing in system LSI differs by
application, and the overall volume of handled data is rapidly
increasing. As a result, there is growing demand for customizable