Renesas SH7203 Manual De Usuario

REJ06B0734-0100/Rev.1.00 

April 2008 

Page 5 of 17 

This section describes the procedure for making initial settings when the DMAC is to be used to transfer data from 
memory to on-chip peripheral modules. On-chip peripheral module requests are used for transfer requests. A flowchart 
of DMAC initialization is shown in figure 2. For details on registers, refer to the SH7263/SH7203 Group Hardware 
Manual. 

START

END

Set standby control register 2 

(STBCR2)

Set DMA channel control register 

(CHCRn)

Set DMA source address control 

register (SARn)

Set DMA reload source

address register (RSARn)

Set DMA destination address 

register (DARn)

Set DMA reload destination

address register (RDARn)

Set DMA transfer count register 

(DMATCRn)

 Set DMA reload transfer

count register (RDMATCRn)

Set DMA channel control register 

(CHCRn)

Set DMA operation register 

(DMAORn)

Set DMA extension resource selector 

registers (DMARS0 to DMARS3)

Set DMA channel control register 

(CHCRn)

• Enabling clock supply to the DMAC (STBCR2)
  Clear the MSTP8  (module stop 8) bit to 0
    [Function] 

Clock supply to the DMAC

• Disabling DMA transfer (CHCRn)
  Clear the DE (DMA enable) bit to 0
  [Function]  Disable 

DMA 

transfer

• Setting DMA transfer source address (SARn)
    [Function] 

Specify DMA transfer source address

• Setting DMA transfer source reload address (RSARn)
    [Function] 

Specify DMA transfer source address to be reloaded

• Setting DMA transfer destination address (DARn)
    [Function] 

Specify DMA transfer destination address

• Setting DMA transfer destination reload address (RDARn)
    [Function] 

Specify DMA transfer destination address to be reloaded

• Setting the DMA transfer count (DMATCRn)
    [Function] 

Set the DMA transfer count

• Setting the DMA transfer reload count (RDMATCRn)
    [Function] 

Set the DMA transfer count to be reloaded

• Setting the DMA transfer mode (CHCRn)
  Set the TC (transfer count mode) bit
    [Function] 

"0":  Transfer data once for each transfer request

     

 

(When the SCIF or IIC3 is selected as the transfer 
request source)

     

"1":  Transfer data for the count specified in DMATCRn for 

each transfer requests

  Set the RLDSAR (SAR reload function enable/disable) bit
    [Function] 

Enables/disables reload function to SAR and DMATCR

  Set the RLDDAR (DAR reload function enable/disable) bit 

  [Function] 

Enables/disables reload function to DAR and DMATCR

  Set the DM (destination address mode) bits
    [Function] 

Select whether the DMA transfer destination address is 
incremented or decremented

     

Fix/increment/decrement the DMA transfer destination address

  Set the SM (source address mode) bits
    [Function] 

Select whether the DMA transfer source address is 
incremented or decremented

     

Fix/increment/decrement the DMA transfer source address

  Set the RS (resource select) bits to B'1000.
    [Function] 

Select DMA extension resource selector (DMA transfer 
request source)

  Set the TB (transfer bus mode) bit
    [Function] 

Select a DMA transfer bus mode.

   

Cycle-stealing 

mode/burst 

mode

     

Note:  When TC is set to 0, select cycle-stealing mode

  Set the TS (transfer size) bits
    [Function] 

Specify the DMA transfer size

  Set the IE (interrupt enable) bit
  [Function]  Enable/disable 

interrupt 

requests

• Specifying settings for DMA transfer requests from on-chip peripheral 

modules (DMARS0 to DMARS3)

    [Function] 

Select the DMA transfer request source

     

SCIF, IIC3, A/D converter, MTU2, or CMT

• Setting the DMA operation register (DMAOR)
  Read from the AE (address error flag) bit and then clear it to 0
    [Function] 

Clear the address error flag

  Read from the NMIF (NMI flag) bit and then clear it to 0
  [Function]  Clear 

the 

NMI 

flag

  Set the DME (DMA master enable) bit to 1
    [Function] 

Enable DMA transfer on all the channels

• Enablling DMA transfer (CHCRn)
  Set the DE (DMA enable) bit to 1
  [Function]  Start 

DMA 

transfer

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]