Renesas 4514 Manual De Usuario
4513/4514 Group User’s Manual
APPLICATION
2-3
2.1 I/O pins
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Port P3
Port P3 is a 4-bit I/O port for the 4514 Group, and a 2-bit I/O port for the 4513 Group.
Port P3 is a 4-bit I/O port for the 4514 Group, and a 2-bit I/O port for the 4513 Group.
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Input/output of port P3
●
●
●
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Data input to port P3
Set the output latch of specified port P3i (i=0 to 3) to “1” with the OP3A instruction. If the output
latch is set to “0,” “L” level is input.
The state of port P3 is transferred to register A when the IAP3 instruction is executed.
However, A
latch is set to “0,” “L” level is input.
The state of port P3 is transferred to register A when the IAP3 instruction is executed.
However, A
2
and A
3
are undefined in the 4513 Group.
Data output from port P3
The contents of register A is output to port P3 with the OP3A instruction.
The output structure is an N-channel open-drain.
The contents of register A is output to port P3 with the OP3A instruction.
The output structure is an N-channel open-drain.
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Port P4 (The 4513 Group does not have this port.)
Port P4 is a 4-bit I/O port.
Port P4 is a 4-bit I/O port.
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Input/output of port P4
Ports P4
0
–P4
3
are also used as A
IN4
–A
IN7
. Therefore, when P4
0
/A
IN4
–P4
3
/A
IN7
are used as port
P4, set corresponding bits of A-D control register Q2 to “0”.
●
Data input to port P4
Set the output latch of specified port P4i (i=0 to 3) to “1” with the OP4A instruction. If the output
latch is set to “0,” “L” level is input.
The state of port P4 is transferred to register A when the IAP4 instruction is executed.
latch is set to “0,” “L” level is input.
The state of port P4 is transferred to register A when the IAP4 instruction is executed.
Data output from port P4
The contents of register A is output to port P4 with the OP4A instruction.
The output structure is an N-channel open-drain.
The contents of register A is output to port P4 with the OP4A instruction.
The output structure is an N-channel open-drain.
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Port P5 (The 4513 Group does not have this port.)
Port P5 is a 4-bit I/O port.
Port P5 is a 4-bit I/O port.
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Input/output of port P5
Port P5 has direction register FR0 to input/output by the bit.
●
Data input to port P5
Set the bit of register FR0i(i=0 to 3) corresponding to specified port P5i (i=0 to 3) to “0.” When
the register FR0 is set to “1,” the value of output latch is input.
The state of port P5 is transferred to register A when the IAP5 instruction is executed.
the register FR0 is set to “1,” the value of output latch is input.
The state of port P5 is transferred to register A when the IAP5 instruction is executed.
Data output from port P5
Set the bit of register FR0i(i=0 to 3) corresponding to specified port P5i (i=0 to 3) to “1.” When
the register FR0 is set to “0,” specified port P5i is in the high-impedance state.
The contents of register A is output to port P5 with the OP5A instruction.
The output structure is CMOS.
Set the bit of register FR0i(i=0 to 3) corresponding to specified port P5i (i=0 to 3) to “1.” When
the register FR0 is set to “0,” specified port P5i is in the high-impedance state.
The contents of register A is output to port P5 with the OP5A instruction.
The output structure is CMOS.