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APPLICATION
2.2 Interrupts
2-24
4513/4514 Group User’s Manual
Fig. 2.2.8 Timer 4 constant period interrupt setting example
0
b3
b0
 Disable Interrupts
Timer 4 interrupt is temporarily disabled.
Interrupt enable flag INTE
Interrupt control register V2
“0”
All interrupts disabled (DI instruction)
Timer 4 interrupt occurrence disabled 
(TV2A instruction)
b3
b0
0 1
 Stop Timer Operation
Timer 4, timer 3 and prescaler are temporarily stopped.
Dividing ratio of prescaler is selected.
Timer control register W1
Prescaler stop (TW1A instruction)
Prescaler divided by 16 selected
Timer 3 stop (TW3A instruction)
Prescaler selected for count source
Timer 4 stop (TW4A instruction)
Timer 3 underflow signal selected for count source
b3
b0
0
1
0
Timer control register W3
b3
b0
0
0
0
Timer control register W4
 Set Timer Value
Timer 3 and timer 4 count times are set. (The formula is shown 
A below.)
Timer 3 reload register R3
Timer 4 reload register R4
“52
16
“F9
16
Timer count value 82 set (T3AB instruction)
Timer count value 249 set (T4AB instruction)
 Clear Interrupt Request
Timer 4 interrupt activated condition is cleared.
Timer 4 interrupt request flag T4F “0”
Timer 4 interrupt activated condition cleared 
(SNZT4 instruction)
Note when the interrupt request is cleared
When 
 is executed, considering the skip of the next instruction according to the 
interrupt request flag T4F, insert the NOP instruction after the SNZT4 instruction.
b3
b0
0
1
1
 Start Timer 4 Operation
Timer 4, timer 3 and prescaler temporarily stopped are restarted.
Timer control register W3
Timer 4 operation start (TW4A instruction)
Timer 3 operation start (TW3A instruction)
Prescaler operation start (TW1A instruction)
b3
b0
1 1
Timer control register W1
✕ ✕
Timer control register W4
b3
b0
0
1
0
b3
b0
1
 Enable Interrupts
The timer 4 interrupt which is temporarily disabled is enabled.
AAAAAA
AAAAAA
Interrupt control register V2
Interrupt enable flag INTE
“1”
Timer 4 interrupt occurrence enabled 
(TV2A instruction)
All interrupts enabled (EI instruction)
Constant period interrupt execution start
A The prescaler dividing ratio, time 3 count value and timer 4 count value to make the interrupt occur 
every 250 ms are set as follows.
250 ms 
 (4.0 MHz)
 
3
16
(82+1)
 (249+1)
–1
System clock Instruction 
clock
Prescaler 
dividing
ratio
Timer 3
count 
value
Timer 4
count 
value
”: it can be “0” or “1.”