Renesas HD6417641 Manual De Usuario
Section 1 Overview
Rev. 4.00 Sep. 14, 2005 Page 1 of 982
REJ09B0023-0400
Section 1 Overview
This LSI is a single-chip RISC microprocessor that integrates a Renesas Technology original 32-
bit SuperH RISC engine architecture CPU with a digital signal processing (DSP) extension as its
core, with 16-kbyte of cache memory, 16-kbyte of an on-chip X/Y memory, and peripheral
functions required for system configuration such as an interrupt controller. This LSI comes in 256-
pin package.
bit SuperH RISC engine architecture CPU with a digital signal processing (DSP) extension as its
core, with 16-kbyte of cache memory, 16-kbyte of an on-chip X/Y memory, and peripheral
functions required for system configuration such as an interrupt controller. This LSI comes in 256-
pin package.
High-speed data transfers can be formed by an on-chip direct memory access controller (DMAC),
and an external memory access support function enables direct connection to different kinds of
memory. This LSI also supports powerful peripheral functions such as USB function and serial
communication interface with FIFO.
and an external memory access support function enables direct connection to different kinds of
memory. This LSI also supports powerful peripheral functions such as USB function and serial
communication interface with FIFO.
1.1 Features
The features of this LSI are listed in table 1.1.
Table 1.1
Features
Items Specification
CPU
• Renesas Technology original SuperH architecture
• Compatible with SH-1, SH-2 and SH-3 at object code level
• 32-bit internal data bus
• Support of an abundant register-set
• Compatible with SH-1, SH-2 and SH-3 at object code level
• 32-bit internal data bus
• Support of an abundant register-set
Sixteen 32-bit general registers (eight 32-bit bank registers)
Eight 32-bit control registers
Four 32-bit system registers
Eight 32-bit control registers
Four 32-bit system registers
• RISC-type instruction set
Instruction length: 16-bit fixed length for improved code efficiency
Load/store architecture
Delayed branch instructions
Instruction set based on C language
Load/store architecture
Delayed branch instructions
Instruction set based on C language
• Instruction execution time: one instruction/cycle for basic instructions
• Logical address space: 4Gbytes
• Five-stage pipeline
• Logical address space: 4Gbytes
• Five-stage pipeline