Renesas HD6417641 Manual De Usuario
Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 742 of 982
REJ09B0023-0400
19.5
SCIF Interrupts and DMAC
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive-data-full (RXI), and break (BRI).
receive-data-full (RXI), and break (BRI).
Table 19.11 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When TXI request is enabled by TIE bit and the TDFE flag in the serial status register (SCFSR) is
set to 1, a TXI interrupt request and transmit FIFO data empty DMA transfer request are
generated. When TXI request is disabled by TIE bit and the TDFE flag is set to 1, transmit FIFO
data empty DMA transfer request is generated. The DMAC can be activated and data transfer
performed by the transmit FIFO data empty DMA transfer request.
set to 1, a TXI interrupt request and transmit FIFO data empty DMA transfer request are
generated. When TXI request is disabled by TIE bit and the TDFE flag is set to 1, transmit FIFO
data empty DMA transfer request is generated. The DMAC can be activated and data transfer
performed by the transmit FIFO data empty DMA transfer request.
When RXI request is enabled by RIE bit and the RDF or DR flag in SCFSR is set to 1, an RXI
interrupt request and receive FIFO data full DMA transfer request are generated. When RXI
request is disabled by RIE bit and the RDF or DR flag in SCFSR is set to 1, receive FIFO data full
DMA transfer request is generated. The DMAC can be activated and data transfer performed by
the receive FIFO data full DMA transfer request. The RXI interrupt request or receive FIFO data
full DMA transfer request caused by DR flag is generated only in asynchronous mode.
interrupt request and receive FIFO data full DMA transfer request are generated. When RXI
request is disabled by RIE bit and the RDF or DR flag in SCFSR is set to 1, receive FIFO data full
DMA transfer request is generated. The DMAC can be activated and data transfer performed by
the receive FIFO data full DMA transfer request. The RXI interrupt request or receive FIFO data
full DMA transfer request caused by DR flag is generated only in asynchronous mode.
When the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1, a BRI interrupt request is
generated.
generated.
When the ER flag in SCFSR is set to 1, an ERI interrupt request is generated.
When transmitting or receiving data are transferred by DMAC, DMAC should be set enable at
first, and then SCIF should be set enable. SCIF should be set not to request RXI or TXI interrupt
to INTC. If SCIF is set to request the interrupt, DMA transfer clears the request to INTC
independently of interrupt handling program.
first, and then SCIF should be set enable. SCIF should be set not to request RXI or TXI interrupt
to INTC. If SCIF is set to request the interrupt, DMA transfer clears the request to INTC
independently of interrupt handling program.
When the RIE bit is set to 0 and the REIE bit is set to 1, SCIF request ERI interrupt and BRI
interrupt without requesting RXI interrupt.
interrupt without requesting RXI interrupt.
The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that
there is receive data in SCFRDR.
there is receive data in SCFRDR.