Renesas HD64F2111B Manual De Usuario

Rev. 1.00, 05/04, page 414 of 544 

 

A block diagram of the A/D converter is shown in figure 16.1. 

Module data bus

Control circuit

Internal data bus

10-bit D/A

Comparator

+

Sample-and-hold

circuit

φ

/16

ADI interrupt signal

A
D
C
S
R

A
D
C
R

A
D
D
R
D

A
D
D
R
C

A
D
D
R
B

A
D
D
R
A

Successive approximations 

register

[Legend]

ADCR: 

A/D control register

ADCSR: A/D control/status register

ADDRA:  A/D data register A

ADDRB:  A/D data register B

ADDRC:  A/D data register C

ADDRD:  A/D data register D

ADTRG

Conversion start trigger from 8-bit timer

φ

/8

AV

CC

 

AV

SS

AV

ref

Multiplexer

Bus interface

AN0

AN1

AN2

AN3

AN4

AN5