Renesas M16C/6N4 Manual De Usuario
M306NKT-EPB User’s Manual
4. Hardware Specifications
REJ10J0519-0200 Rev.2.00 Oct. 16, 2006
Page 84 of 104
IMPORTANT
Notes on Pullup Control:
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Because this product emulates some I/O ports (P0 to P5, P10), you can not pullup ports P0 to P5 by the pullup
control registers, Install the included resistor arrays (51kΩ) as necessary.
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The initial value of pullup control register 1 PUR1 of this product is different from that of an actual MCU.
When a Vcc level is input to pin CNVss, the value of an actual MCU is “02h” (bit 1 PU11 is “1”), while that of
this product is “00h”.
this product is “00h”.
Note on Setting "1" to Protect Bit 2 (PCR2) with Sub Clock:
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When the CPU clock is set to the sub-clock (low-speed mode or low power dissipation mode), even if you
enable the PRC2 bit, writing to the register protected by the PRC2 bit (PD7, PD9, S3C, S4C, S5C and S6C)
cannot be done properly. When you enable the PRC2 bit and write to the register protected by the PRC2, do not
set the CPU clock to the sub-clock.
cannot be done properly. When you enable the PRC2 bit and write to the register protected by the PRC2, do not
set the CPU clock to the sub-clock.
Note on Setting "1" to Protect Bit 2 (PRC2) in Division by 2 Mode:
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Under the following conditions, even if you enable the PRC2 bit, writing to the register protected by the PRC2
bit (PD7, PD9, S3C, S4C, S5C and S6C) cannot be done properly.
(1) Between when stop mode is released and when a hardware reset is executed
(2) Between when low power dissipation mode is enabled and when a hardware reset is executed
Therefore, if the condition (1) or (2) applies, when you enable the PRC2 bit and write to the register protected
(2) Between when low power dissipation mode is enabled and when a hardware reset is executed
Therefore, if the condition (1) or (2) applies, when you enable the PRC2 bit and write to the register protected
by the PRC2 (PD7, PD9, S3C, S4C, S5C and S6C), do not set the CPU clock to the main clock in division by 2
mode.
mode.
Note on the Input Thresholds for the Pins P1_5/D13/INT3, P1_6/D14/INT4 and P1_7/D15/INT5
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With this product, regarding pins P1_5/D13/INT3, P1_6/D14/INT4 and P1_7/D15/INT5, a device which port or
data bus inputs to and a device which INT interrupt inputs to are different as follows:
- Device which port or data bus inputs to: Port emulation FPGA (input level: TTL)
- Device which INT interrupt inputs to: Evaluation MCU for emulating peripheral functions (input level:
CMOS Schmidt)
Therefore, the port input level can be read as “H” immediately after an INT interrupt (falling), and the port
input level can be read as “H” immediately before an INT interrupt (rising).
input level can be read as “H” immediately before an INT interrupt (rising).
Note on Input Level for KI0# to KI3#:
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With this product, the KI0# to KI3# are TTL input level using the port emulation FPGA although these are the
CMOS Schmidt input level with the actual MCU. Therefore, the wrong interrupt may occur near the threshold
of the TTL level (2.0V to 0.8V) when the input signal is slow changing.
of the TTL level (2.0V to 0.8V) when the input signal is slow changing.
Note on Final Evaluation:
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Be sure to evaluate your system with an evaluation MCU. Before starting mask production, evaluate your
system and make final confirmation with a CS (Commercial Sample) version MCU.