Renesas M30100T3-RPD-E Manual De Usuario
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Note on Instructions that Access the Single-step Interrupt Vector Area:
• Do not perform the below debugging operations with the single step interrupt vector area (addresses
FFFECh--FFFEFh).
(1) Step execution of instructions that access the single step interrupt vector area
(2) Program execution from the instruction accessing the single step interrupt vector area when
a software breakpoint is set at the instruction
IMPORTANT
Note on Differences between the Actual MCU and Emulator:
• Operations of the emulator system differ from those of actual MCUs as listed below.
(1) Reset condition
Set the rise time (0.2 Vcc = 0.8 Vcc) to 1
µs or less.
(2) Initial values of internal resource data at power-on
(3) Internal memories (ROM and RAM) capacities, etc.
With this emulator system, "INT" (emulation memory ON) is the default for mapping areas
other than the SFR area (addresses 000h--3FFh). For this reason, the emulation memories can
be read and written into in an area other than the SFR, internal RAM or internal ROM area.
other than the SFR area (addresses 000h--3FFh). For this reason, the emulation memories can
be read and written into in an area other than the SFR, internal RAM or internal ROM area.
(4) Oscillator circuit
• Make note of the fact that in the oscillator circuit where an oscillator is connected between
pins X
IN
and X
OUT
, oscillation does not occur because a flexible cable, buffer IC and other
devices are used between the evaluation MCU and the target system. It is same for sub-clock
oscillator circuits (X
oscillator circuits (X
CIN
and X
COUT
).
• For notes on when using the oscillator circuit on the target system, refer to "3.2 (2) Using
the Oscillator Circuit on the Target System" (page 24).
(5) DBC, single-step and BRK instruction interrupt vector table addresses
It is possible to download to DBC, single-step and BRK instruction interrupt vector table
addresses. However, because the emulator system uses these areas, data different from the
expected value is read out (see Table 1.1).
addresses. However, because the emulator system uses these areas, data different from the
expected value is read out (see Table 1.1).
Table 1.1 Vector table addresses for the emulator
Factor to interrupt
Vector table addresses
Data for reading
DBC*
1
FFFF4h--FFFF7h
Indefinite
Single-step*
1
FFFECh--FFFEFh
Indefinite
BRK instruction
FFFE4h--FFFE7h
Indefinite
*1: Interrupts used for the debugger only
(6) A-D conversion
The characteristics of A-D converter differ from those of an actual MCU because there are a
flexible cable, pitch converter and other devices between the evaluation MCU and the target
system. Make the final evaluation of the A-D converter with the actual MCU.
flexible cable, pitch converter and other devices between the evaluation MCU and the target
system. Make the final evaluation of the A-D converter with the actual MCU.
(7) D-A conversion
The characteristics of D-A converter differ from those of an actual MCU because there are a
flexible cable, pitch converter and other devices between the evaluation MCU and the target
system. Make the final evaluation of the D-A converter with the actual MCU.
flexible cable, pitch converter and other devices between the evaluation MCU and the target
system. Make the final evaluation of the D-A converter with the actual MCU.