Intel 820E Manual De Usuario

Design Guide 

 

147 

The transmission line package models must be inserted between the output of the buffer and the net it is 
driving. Likewise, the package model must also be placed between a net and the input of a receiver 
model. This is performed, generally, by editing the simulator’s net description or topology file. 

Intel has found wide variation in noise margins when varying the stub impedance and the PCB’s Z0 and 
S0. Intel therefore recommends that PCB parameters be controlled as tightly as possible, with sampling 
of the allowable Z0 and S0 simulated. The Intel PGA370-socketed Pentium III processor’s nominal 
effective line impedance (Z

EFF

) is 60 

Ω

 ± 15%. Intel recommends a baseboard nominal effective line 

impedance of 60 

Ω

 ± 15% for the recommended layout guidelines to be effective. Intel also recommends 

both running uncoupled simulations using the Z

0

 of the package stubs as well as performing fully coupled 

simulations if increased accuracy is needed or desired. Accounting for crosstalk within the device 
package by varying the stub impedance was investigated and was not found to be sufficiently accurate. 
This led to the development of full-package models for the component packages. 

Estimate the number of layers that will be required. Then determine the expected interconnect distances 
between each component on the AGTL+ bus. Using the estimated interconnect distances, verify that the 
placement can support the system timing requirements. 

The required bus frequency and the maximum flight time propagation delay on the PCB determine the 
maximum network length between the bus agents. The minimum network length is independent of the 
required bus frequency.  

Table 52 and Table 53 assume values for CLKSKEW and CLKJITTER parameters that are controlled by 
the system designer. To minimize the system clock skew, Intel recommends clock buffers that allow their 
outputs to be tied together. Intel strongly recommends running analog simulations to ensure that each 
design has adequate noise and timing margins. 

Route the board satisfying the estimated space and timing requirements. Also stay within the solution 
space set from the pre-layout sweeps. Estimate the printed circuit board parameters from the placement 
and other information, including the following general guidelines: 

• 

Distribute V

TT

 with a power plane or a partial power plane. If this cannot be accomplished, use as 

wide a trace as possible and route the V

TT 

trace with the same topology as the AGTL+ traces. 

• 

Keep the overall length of the bus as short as possible, but do not forget the minimum component-
to-component distances required to meet hold times. 

• 

Plan to minimize crosstalk with the following guidelines developed for the example topology given. 
(Signal spacing recommendations were based on fully coupled simulations. Spacing may be 
decreased based upon the amount of coupled length.) 

 

Use a spacing-to-line width-to-dielectric thickness ratio of at least 3:1:2. If 

ε

r 

= 4.5, this should 

limit coupling to 3.4%. 

 

Minimize the dielectric process variation used in PCB fabrication. 

 

Eliminate parallel traces between layers not separated by a power or ground plane. 

Table 54contains the trace width:space ratios assumed for this topology. The crosstalk cases considered 
in this guideline involve three types: intragroup AGTL+, intergroup AGTL+, and AGTL+ to non-