Intel 820E Manual De Usuario

Intel

Intel

®

820E Chipset

R

Design Guide

3

Contents

Introduction ................................................................................................................................ 13

About This Design Guide .............................................................................................. 13

Reference Documents................................................................................................... 14

System Overview........................................................................................................... 15

Chipset Components................................................................................... 16

Bandwidth Summary ................................................................................... 17

System Configuration .................................................................................. 18

Platform Initiatives ......................................................................................................... 20

Direct Rambus RAM (RDRAM*) ................................................................. 20

Streaming SIMD Extensions ....................................................................... 20

...................................................................................................... 20

Hub Interface............................................................................................... 20

Integrated LAN Controller............................................................................ 21

Ultra ATA/100 Support ................................................................................ 21

Expanded USB Support .............................................................................. 21

Manageability .............................................................................................. 21

AC’97 ........................................................................................................ 23

Low-Pin-Count (LPC) Interface ................................................................... 25

Layout/Routing Guidelines ......................................................................................................... 27

General Recommendations........................................................................................... 27

Component Quadrant Layout ........................................................................................ 27

820E Chipset Component Placement.................................................................. 29

Core Chipset Routing Recommendations ..................................................................... 30

Source-Synchronous Strobing....................................................................................... 32

Differential Clocking/Strobing ........................................................................................ 33

Direct RDRAM* Interface .............................................................................................. 33

Stack-Up...................................................................................................... 34

Direct RDRAM* Layout Guidelines.............................................................. 34

RSL Routing ................................................................................... 35

RSL Termination............................................................................. 38

Direct RDRAM* Ground Plane Reference...................................... 39

Direct RDRAM* Connector Compensation..................................... 41

2.7.2.4.1.

Direct RDRAM* Channel Connector Compensation
Enhancement Recommendation .................................. 47

RSL Signal Layer Alternation.......................................................... 49

Length Matching Methods .............................................................. 50

Via Compensation .......................................................................... 52

Length Matching and Via Compensation Example......................... 52

Direct RDRAM* Reference Voltage............................................................. 54

High-Speed CMOS Routing ........................................................................ 54

SIO Routing .................................................................................... 55

Suspend-to-RAM Shunt Transistor................................................. 56

Direct RDRAM* Clock Routing.................................................................... 57

Direct RDRAM* Design Checklist ............................................................... 57

AGP 2.0 ......................................................................................................................... 60

AGP Interface Signal Groups ...................................................................... 60

1× Timing Domain Routing Guidelines........................................................ 62