Cisco Systems VCO/4K Manual De Usuario
4-9
Cisco VCO/4K Mechanical Assemblies
78-10334-03
Chapter 4
Storage/Control I/O Module
Description
Serial Ports 3 and 4
Serial Ports 3 and 4 are available for Serial I/O (SIO) links between the system and a host computer.
These standard female DB-25 ports carry Asynchronous Data Link Control (ADLC) protocol signals
between the host and the system over EIA/TIA-232 cables. Pin and signal assignments for port 3 is the
same as Serial Ports 1 and 2. Refer to Table 4-2 for port 4 pin and signal assignments.
These standard female DB-25 ports carry Asynchronous Data Link Control (ADLC) protocol signals
between the host and the system over EIA/TIA-232 cables. Pin and signal assignments for port 3 is the
same as Serial Ports 1 and 2. Refer to Table 4-2 for port 4 pin and signal assignments.
Wiring conventions for physically connecting a host computer to a SIO port are provided in the Cisco
VCO/4K Hardware Installation Guide. Jumpers on the Storage/Control I/O Module allow Serial Ports 3
and 4 to be configured as modem (DCE) terminations for connection to a terminal or configured as
terminal (DTE) terminations for connection to a modem. Refer to the “Serial Ports 1 Through 4 and
Jumper Settings” section on page 4-11 for more information on jumper configurations.
VCO/4K Hardware Installation Guide. Jumpers on the Storage/Control I/O Module allow Serial Ports 3
and 4 to be configured as modem (DCE) terminations for connection to a terminal or configured as
terminal (DTE) terminations for connection to a modem. Refer to the “Serial Ports 1 Through 4 and
Jumper Settings” section on page 4-11 for more information on jumper configurations.
Data communication parameters for each host link must be defined in the system database using the Host
Configuration screen following system power-on. Refer to the Cisco VCO/4K System Administrator’s
Guide for instructions on defining host links.
Configuration screen following system power-on. Refer to the Cisco VCO/4K System Administrator’s
Guide for instructions on defining host links.
Ethernet Interface
The CPU employs a Local Area Network Controller for Ethernet (LANCE) to implement an Ethernet
transceiver interface. The balanced transceiver signal lines from the CPU are coupled to an onboard
transformer to signal lines that go through the SWI, Outer B/P and control midplane cards, and terminate
on the industry-standard DB-15 connector on the Storage/Control I/O Module faceplate. Pin and signal
assignments for this DB-15 port are listed in Table 4-3.
transceiver interface. The balanced transceiver signal lines from the CPU are coupled to an onboard
transformer to signal lines that go through the SWI, Outer B/P and control midplane cards, and terminate
on the industry-standard DB-15 connector on the Storage/Control I/O Module faceplate. Pin and signal
assignments for this DB-15 port are listed in Table 4-3.
Table 4-2
Serial Ports 3 and 4 Pin and Signal Assignments
1
1.
All pins not identified are no-connection.
Pin
Signal Name
Description/Direction
2
TxD
Transmit Data (terminal to modem)
3
RxD
Receive Data (modem to terminal)
4
RTS
Request to Send (terminal to modem)
5
CTS
Clear to Send (modem to terminal)
6
DSR
Data Set Ready (modem to terminal)
7
GND
Chassis Ground
8
DCD
Data Carrier Detect (modem to terminal)
15
RTxC
Tx Clock to output data (terminal to modem)
17
RRxC
Rx Clock to input data (terminal to modem)
20
DTR
Data Terminal Ready (terminal to modem)
24
TTxC
Tx Clock to output data (terminal to modem)