SMSC LAN9311 Manual De Usuario

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

140

SMSC LAN9311/LAN9311i

 

 illustrates the process required to perform an EEPROM read or write operation.

The I

2

C master implements a low level serial interface (start and stop condition generation, data bit

transmission and reception, acknowledge generation and reception) for connection to I

2

C EEPROMs,

and consists of a data wire (EE_SDA) and a serial clock (EE_SCL). The serial clock is driven by the
master, while the data wire is bi-directional. Both signals are open-drain and require external pull-up
resistors.

The serial clock is also used as an input as it can be held low by the slave device in order to wait-
state the data cycle. Once the slave has data available or is ready to receive, it will release the clock.
Assuming the masters clock low time is also expired, the clock will rise and the cycle will continue. In
the event that the slave device holds the clock low for more than 30mS, the current command
sequence is aborted and the EPC_TIMEOUT bit in the 

 is

set. Both the clock and data signals have Schmitt trigger inputs and digital input filters. The digital filters
reject pulses that are less than 100nS. 

Since the I

2

C master is designed to access EEPROM only, multi-master arbitration is not

supported.

Based on the configuration strap eeprom_size_strap, various sized I

2

C EEPROMs are supported. The

varying size ranges are supported by additional bits in the address field (EPC_ADDRESS) of the

. Within each size range, the largest EEPROM uses all the

address bits, while the smaller EEPROMs treat the upper address bits as don’t cares. The EEPROM