SMSC LAN9311 Manual De Usuario
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
223
Revision 1.4 (08-19-08)
DATASHEET
14.2.5.22
1588 Configuration Register (1588_CONFIG)
This read/write register is responsible for the configuration of the 1588 timestamps for all ports.
Offset:
194h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31
Master/Slave Port 2 (M_nS_2)
When set, Port 2 is a time clock master and captures timestamps when a
Sync packet is transmitted and when a Delay_Req is received. When
cleared, Port 2 is a time clock slave and captures timestamps when a
Delay_Req packet is transmitted and when a Sync packet is received.
When set, Port 2 is a time clock master and captures timestamps when a
Sync packet is transmitted and when a Delay_Req is received. When
cleared, Port 2 is a time clock slave and captures timestamps when a
Delay_Req packet is transmitted and when a Sync packet is received.
R/W
0b
30
Primary MAC Address Enable Port 2 (MAC_PRI_EN_2)
This bit enables/disables the primary MAC address on Port 2.
This bit enables/disables the primary MAC address on Port 2.
0: Disables primary MAC address on Port 2
1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 2
1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 2
R/W
1b
29
Alternate MAC Address 1 Enable Port 2 (MAC_ALT1_EN_2)
This bit enables/disables the alternate MAC address 1 on Port 2.
This bit enables/disables the alternate MAC address 1 on Port 2.
0: Disables alternate MAC address on Port 2
1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 2
1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 2
R/W
0b
28
Alternate MAC Address 2 Enable Port 2 (MAC_ALT2_EN_2)
This bit enables/disables the alternate MAC address 2 on Port 2.
This bit enables/disables the alternate MAC address 2 on Port 2.
0: Disables alternate MAC address on Port 2
1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 2
1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 2
R/W
0b
27
Alternate MAC Address 3 Enable Port 2 (MAC_ALT3_EN_2)
This bit enables/disables the alternate MAC address 3 on Port 2.
This bit enables/disables the alternate MAC address 3 on Port 2.
0: Disables alternate MAC address on Port 2
1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 2
1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 2
R/W
0b
26
User Defined MAC Address Enable Port 2 (MAC_USER_EN_2)
This bit enables/disables the auxiliary MAC address on Port 2. The auxiliary
address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO
registers.
This bit enables/disables the auxiliary MAC address on Port 2. The auxiliary
address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO
registers.
0: Disables auxiliary MAC address on Port 2
1: Enables auxiliary MAC address as a PTP address on Port 2
1: Enables auxiliary MAC address as a PTP address on Port 2
R/W
0b
25
Lock Enable RX Port 2 (LOCK_RX_2)
This bit enables/disables the RX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX
interrupt for Port 2 is already set due to a previous capture.
This bit enables/disables the RX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX
interrupt for Port 2 is already set due to a previous capture.
0: Disables RX Port 2 Lock
1: Enables RX Port 2 Lock
1: Enables RX Port 2 Lock
R/W
1b
24
Lock Enable TX Port 2 (LOCK_TX_2)
This bit enables/disables the TX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX
interrupt for Port 2 is already set due to a previous capture.
This bit enables/disables the TX lock. This lock prevents a 1588 capture
from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX
interrupt for Port 2 is already set due to a previous capture.
0: Disables TX Port 2 Lock
1: Enables TX Port 2 Lock
1: Enables TX Port 2 Lock
R/W
1b
23
Master/Slave Port 1 (M_nS_1)
When set, Port 1 is a time clock master and captures timestamps when a
Sync packet is transmitted and when a Delay_Req is received. When
cleared, Port 1 is a time clock slave and captures timestamps when a
Delay_Req packet is transmitted and when a Sync packet is received.
When set, Port 1 is a time clock master and captures timestamps when a
Sync packet is transmitted and when a Delay_Req is received. When
cleared, Port 1 is a time clock slave and captures timestamps when a
Delay_Req packet is transmitted and when a Sync packet is received.
R/W
0b