SMSC LAN9311 Manual De Usuario
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
367
Revision 1.4 (08-19-08)
DATASHEET
14.5.2.44
Port x MAC Interrupt Pending Register (MAC_IPR_x)
This read-only register contains the pending Port x interrupts. A set bit indicates an interrupt has been
triggered. All interrupts in this register may be masked via the
triggered. All interrupts in this register may be masked via the
register. Refer to
Note:
There are no possible Port x interrupt conditions available. This register exists for future use.
Register #:
Port0: 0481h
Size:
32 bits
Port1: 0881h
Port2: 0C81h
Port2: 0C81h
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
RESERVED
RO
-