SMSC LAN9311 Manual De Usuario

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

40

SMSC LAN9311/LAN9311i

 

Note: When using the Reset bit to reset the Port 1 PHY, register bits designated as NASR are not

reset.

 for additional information on Port 1 PHY resets.

A Virtual PHY reset is performed by setting the VPHY_RST bit of the 

, or Reset in

the 

. No other modules of the

LAN9311/LAN9311i are affected by this reset.

Virtual PHY reset completion can be determined by polling the VPHY_RST bit in the 

, the VPHY_RST bit in the 

,

or the Reset bit in the 

 until it clears. Under

normal conditions, the VPHY_RST and Reset bit will clear approximately 1uS after the Virtual PHY
reset occurrence.

 for additional information on Virtual PHY

resets.

Configuration straps allow various features of the LAN9311/LAN9311i to be automatically configured
to user defined values. Configuration straps can be organized into two main categories: hard-straps
and soft-straps. Both hard-straps and soft-straps are latched upon Power-On Reset (POR) or pin reset
(nRST). The primary difference between these strap types is that soft-strap default values can be
overridden by the EEPROM Loader, while hard-straps cannot.

Configuration straps which have a corresponding external pin include internal resistors in order to
prevent the signal from floating when unconnected. If a particular configuration strap is connected to
a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to
ensure that it reaches the required voltage level prior to latching. The internal resistor can also be
overridden by the addition of an external resistor.

Note: The system designer must guarantee that configuration strap pins meet the timing

requirements specified in 

.

If configuration strap pins are not at the correct voltage level prior to being latched, the
LAN9311/LAN9311i may capture incorrect strap values.

Soft-strap values are latched on the release of POR or nRST and are overridden by values from the
EEPROM Loader (when an EEPROM is present). These straps are used as direct configuration values
or as defaults for CPU registers. Some, but not all, soft-straps have an associated pin. Those that do
not have an associated pin, have a tie off default value. All soft-strap values can be overridden by the
EEPROM Loader. 

 provides a list of all soft-straps and their associated pin or default value.

Straps which have an associated pin are also fully defined in 

. Refer to 

 for information

on the operation of the EEPROM Loader and the loading of strap values.

Upon setting the DIGITAL_RST bit in the 

 or upon issuing a

RELOAD command via the 

, these straps return to their

original latched (non-overridden) values if an EEPROM is no longer attached or has been erased. The
associated pins are not re-sampled. (i.e. The value latched on the pin during the last POR or nRST
will be used, not the value on the pin during the digital reset or RELOAD command issuance). If it is
desired to re-latch the current configuration strap pin values, a POR or nRST must be issued.