SMSC LAN9311 Manual De Usuario
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
51
Revision 1.4 (08-19-08)
DATASHEET
The following sections detail each category of interrupts and their related registers. Refer to
for bit-level definitions of all interrupt registers.
5.2.1
1588 Time Stamp Interrupts
Multiple 1588 Time Stamp interrupt sources are provided by the LAN9311/LAN9311i. The top-level
1588_EVNT (bit 29) of the
1588_EVNT (bit 29) of the
event occurred in the
The
provides enabling/disabling and
status of all 1588 interrupt conditions. These include TX/RX 1588 clock capture indication on Ports
2,1,0, 1588 clock capture for GPIO[8:9] events, as well as 1588 timer interrupt indication.
2,1,0, 1588 clock capture for GPIO[8:9] events, as well as 1588 timer interrupt indication.
In order for a 1588 interrupt event to trigger the external IRQ interrupt pin, the desired 1588 interrupt
event must be enabled in the
event must be enabled in the
, bit 29
(1588_EVNT_EN) of the
must be set, and IRQ output must be
enabled via bit 8 (IRQ_EN) of the
5.2.2
Switch Fabric Interrupts
Multiple Switch Fabric interrupt sources are provided by the LAN9311/LAN9311i in a three-tiered
register structure as shown in
register structure as shown in
. The top-level SWITCH_INT (bit 28) of the
provides indication that a Switch Fabric interrupt event occurred in the
.
In turn, the
provide status and enabling/disabling of all Switch Fabric sub-modules interrupts
(Buffer Manager, Switch Engine, and Port 2,1,0 MACs).
The low-level Switch Fabric sub-module interrupt pending and mask registers of the Buffer Manager,
Switch Engine, and Port 2,1,0 MACs provide multiple interrupt sources from their respective sub-
modules. These low-level registers provide the following interrupt sources:
Switch Engine, and Port 2,1,0 MACs provide multiple interrupt sources from their respective sub-
modules. These low-level registers provide the following interrupt sources:
Buffer Manager (
and
)
—Status B Pending
—Status A Pending
—Status A Pending
Switch Engine (
—Interrupt Pending
Port 2,1,0 MACs (
and
)
—No currently supported interrupt sources. These registers are reserved for future use.
In order for a Switch Fabric interrupt event to trigger the external IRQ interrupt pin, the following must
be configured:
be configured:
The desired Switch Fabric sub-module interrupt event must be enabled in the corresponding mask
register (
register (
for the Buffer Manager,
for the Switch Engine, and/or
for the Port 2,1,0 MACs)
The desired Switch Fabric sub-module interrupt event must be enabled in the
Bit 28 (SWITCH_INT_EN) of the
must be set
IRQ output must be enabled via bit 8 (IRQ_EN) of the
For additional details on the Switch Fabric interrupts, refer to