Intel ECB-862 Manual De Usuario
ECB-862/862L
ECB-862/862L User’s Manual 9
Integrated PCI-mastering dual full-duplex direct-sound AC97-link-compatible
sound system. Hardware soundblaster-pro and hardware-assisted FM blocks are
included for Windows DOS box and real-mode DOS compatibility. Loopback
capability is also implemented for directing mixed audio streams into USB and
1394 speakers for high quality digital audio.
sound system. Hardware soundblaster-pro and hardware-assisted FM blocks are
included for Windows DOS box and real-mode DOS compatibility. Loopback
capability is also implemented for directing mixed audio streams into USB and
1394 speakers for high quality digital audio.
Two game ports and one MIDI port
ECP/EPP-capable parallel port
Standard floppy disk drive interface
Distributed DMA capability for support of ISA legacy DMA over the PCI bus.
Serial IRQ is also supported for docking and non-docking applications.
Serial IRQ is also supported for docking and non-docking applications.
Plug and Play controller that allows complete steerability of all PCI interrupts and
internal interrupts / DMA channels to any interrupt channel. One additional
steerable interrupt channel is provided to allow plug and play and reconfigurability
of on-board peripherals for Windows family compliance.
internal interrupts / DMA channels to any interrupt channel. One additional
steerable interrupt channel is provided to allow plug and play and reconfigurability
of on-board peripherals for Windows family compliance.
Internal I/O APIC (Advanced Programmable Interrupt Controller)
2.3.4 Current PCI Bus Controller
PCI bus is synchronous / pseudo-synchronous to host CPU bus
33 MHz operation on the primary PCI bus
Supports up to five PCI masters
Peer concurrency
Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI
buses active at the same time
buses active at the same time
Zero wait state PCI master and slave burst transfer rate
PCI to system memory data streaming up to 132Mbyte/sec
PCI master snoop ahead and snoop filtering
Six levels (double-words) of CPU to PCI posted write buffers
Byte merging in the write buffers to reduce the number of PCI cycles and to create
further PCI bursting possibilities
further PCI bursting possibilities
Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
Forty-eight levels (double-words) of post write buffers from PCI masters to DRAM
Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI
masters
masters
Supports L1/L2 write-back forward to PCI master read to minimize PCI read latency