Intel 253668-032US Manual De Usuario
Vol. 3 11-9
MEMORY CACHE CONTROL
registers to access UC memory that may have read or write side
effects.
effects.
•
Uncacheable (UC-) — Has same characteristics as the strong uncacheable (UC)
memory type, except that this memory type can be overridden by programming
the MTRRs for the WC memory type. This memory type is available in processor
families starting from the Pentium III processors and can only be selected through
the PAT.
memory type, except that this memory type can be overridden by programming
the MTRRs for the WC memory type. This memory type is available in processor
families starting from the Pentium III processors and can only be selected through
the PAT.
•
Write Combining (WC) — System memory locations are not cached (as with
uncacheable memory) and coherency is not enforced by the processor’s bus
coherency protocol. Speculative reads are allowed. Writes may be delayed and
combined in the write combining buffer (WC buffer) to reduce memory accesses.
If the WC buffer is partially filled, the writes may be delayed until the next
occurrence of a serializing event; such as, an SFENCE or MFENCE instruction,
CPUID execution, a read or write to uncached memory, an interrupt occurrence,
or a LOCK instruction execution. This type of cache-control is appropriate for
video frame buffers, where the order of writes is unimportant as long as the
writes update memory so they can be seen on the graphics display. See Section
11.3.1, “Buffering of Write Combining Memory Locations,” for more information
about caching the WC memory type. This memory type is available in the
Pentium Pro and Pentium II processors by programming the MTRRs; or in
processor families starting from the Pentium III processors by programming the
MTRRs or by selecting it through the PAT.
uncacheable memory) and coherency is not enforced by the processor’s bus
coherency protocol. Speculative reads are allowed. Writes may be delayed and
combined in the write combining buffer (WC buffer) to reduce memory accesses.
If the WC buffer is partially filled, the writes may be delayed until the next
occurrence of a serializing event; such as, an SFENCE or MFENCE instruction,
CPUID execution, a read or write to uncached memory, an interrupt occurrence,
or a LOCK instruction execution. This type of cache-control is appropriate for
video frame buffers, where the order of writes is unimportant as long as the
writes update memory so they can be seen on the graphics display. See Section
11.3.1, “Buffering of Write Combining Memory Locations,” for more information
about caching the WC memory type. This memory type is available in the
Pentium Pro and Pentium II processors by programming the MTRRs; or in
processor families starting from the Pentium III processors by programming the
MTRRs or by selecting it through the PAT.
•
Write-through (WT) — Writes and reads to and from system memory are
cached. Reads come from cache lines on cache hits; read misses cause cache
fills. Speculative reads are allowed. All writes are written to a cache line (when
cached. Reads come from cache lines on cache hits; read misses cause cache
fills. Speculative reads are allowed. All writes are written to a cache line (when
Table 11-2. Memory Types and Their Properties
Memory Type and
Mnemonic
Cacheable
Writeback
Cacheable
Allows
Speculative
Reads
Memory Ordering Model
Strong Uncacheable
(UC)
No
No
No
Strong Ordering
Uncacheable (UC-)
No
No
No
Strong Ordering. Can only be
selected through the PAT. Can
be overridden by WC in MTRRs.
Write Combining (WC) No
No
Yes
Weak Ordering. Available by
programming MTRRs or by
selecting it through the PAT.
Write Through (WT)
Yes
No
Yes
Speculative Processor Ordering.
Write Back (WB)
Yes
Yes
Yes
Speculative Processor Ordering.
Write Protected (WP) Yes for
reads; no for
writes
No
Yes
Speculative Processor Ordering.
Available by programming
MTRRs.