Cypress CY7C1992BV18 Manual De Usuario
CY7C1392BV18, CY7C1992BV18
CY7C1393BV18, CY7C1394BV18
CY7C1393BV18, CY7C1394BV18
Document #: 38-05623 Rev. *D
Page 3 of 31
Logic Block Diagram (CY7C1393BV18)
Logic Block Diagram (CY7C1394BV18)
512
K x 18 Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read
Add. Decode
Read Data Reg.
LD
Q
[17:0]
Reg.
Reg.
Reg.
18
36
18
BWS
[1:0]
V
REF
W
rite Add. D
e
cod
e
Write
Data Reg
Data Reg
18
18
19
18
R/W
LD
R/W
CQ
CQ
DOFF
512
K x 18 Array
Write
Data Reg
Data Reg
Control
Logic
C
C
18
256K x 36 Arra
y
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Re
ad Add. Decode
Read Data Reg.
LD
Q
[35:0]
Reg.
Reg.
Reg.
36
72
36
BWS
[3:0]
V
REF
W
rite Add.
Deco
de
Write
Data Reg
Data Reg
36
36
18
36
R/W
LD
R/W
CQ
CQ
DOFF
256K x 36 Arra
y
Write
Data Reg
Data Reg
Control
Logic
C
C
36