Cypress CY7C1992BV18 Manual De Usuario
CY7C1392BV18, CY7C1992BV18
CY7C1393BV18, CY7C1394BV18
CY7C1393BV18, CY7C1394BV18
Document #: 38-05623 Rev. *D
Page 8 of 31
Functional Overview
The CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, and
CY7C1394BV18 are synchronous pipelined Burst SRAMs
equipped with a DDR-II Separate IO interface.
CY7C1394BV18 are synchronous pipelined Burst SRAMs
equipped with a DDR-II Separate IO interface.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing is
referenced to the rising edge of the output clocks (C/C, or K/K
when in single clock mode).
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing is
referenced to the rising edge of the output clocks (C/C, or K/K
when in single clock mode).
All synchronous data inputs (D
[x:0]
) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q
synchronous data outputs (Q
[x:0]
) pass through output registers
controlled by the rising edge of the output clocks (C/C, or K/K
when in single-clock mode).
when in single-clock mode).
All synchronous control (R/W, LD, BWS
[0:X]
) inputs pass through
input registers controlled by the rising edge of the input clock (K).
CY7C1393BV18 is described in the following sections. The
same basic descriptions apply to CY7C1392BV18,
CY7C1992BV18, and CY7C1394BV18.
same basic descriptions apply to CY7C1392BV18,
CY7C1992BV18, and CY7C1394BV18.
Read Operations
The CY7C1393BV18 is organized internally as two arrays of
512K x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W
512K x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W
HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to address inputs is stored in
the read address register. Following the next K clock rise the
corresponding lowest order 18-bit word of data is driven onto the
Q
the read address register. Following the next K clock rise the
corresponding lowest order 18-bit word of data is driven onto the
Q
[17:0]
using C as the output timing reference. On the subse-
quent rising edge of C, the next 18-bit data word is driven onto
the Q
the Q
[17:0]
. The requested data is valid 0.45 ns from the rising
edge of the output clock (C or C, or K and K when in single clock
mode, for 200 MHz and 250 MHz device). Read accesses can
be initiated on every rising edge of the positive input clock (K).
This pipelines the data flow such that data is transferred out of
the device on every rising edge of the output clocks, C/C (or K/K
when in single clock mode).
mode, for 200 MHz and 250 MHz device). Read accesses can
be initiated on every rising edge of the positive input clock (K).
This pipelines the data flow such that data is transferred out of
the device on every rising edge of the output clocks, C/C (or K/K
when in single clock mode).
The CY7C1393BV18 first completes the pending read transac-
tions, when read access is deselected. Synchronous internal
circuitry automatically tri-states the output following the next
rising edge of the positive output clock (C).
tions, when read access is deselected. Synchronous internal
circuitry automatically tri-states the output following the next
rising edge of the positive output clock (C).
Write Operations
Write operations are initiated by asserting R/W
LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise the data presented
to D
address presented to address inputs is stored in the write
address register. On the following K clock rise the data presented
to D
[17:0]
is latched and stored into the 18-bit write data register,
provided BWS
[1:0]
are both asserted active. On the subsequent
rising edge of the negative input clock (K) the information
presented to D
presented to D
[17:0]
is also stored into the write data register,
provided BWS
[1:0]
are both asserted active. The 36 bits of data
are then written into the memory array at the specified location.
Write accesses can be initiated on every rising edge of the
positive input clock (K). This pipelines the data flow such that 18
bits of data can be transferred into the device on every rising
edge of the input clocks (K and K).
Write accesses can be initiated on every rising edge of the
positive input clock (K). This pipelines the data flow such that 18
bits of data can be transferred into the device on every rising
edge of the input clocks (K and K).
When Write access is deselected, the device ignores all inputs
after the pending write operations are completed.
after the pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1393BV18. A
write operation is initiated as described in the
write operation is initiated as described in the
section. The bytes that are written are determined by BWS
0
and
BWS
1
, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read/modify/write operations to a byte write operation.
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read/modify/write operations to a byte write operation.
Single Clock Mode
The CY7C1393BV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, tie C and C HIGH at
power on. This function is a strap option and not alterable during
device operation.
controls both the input and output registers. In this mode the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, tie C and C HIGH at
power on. This function is a strap option and not alterable during
device operation.
DDR Operation
The CY7C1393BV18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
double data rate mode of operation.
through high clock frequencies (achieved through pipelining) and
double data rate mode of operation.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information must be stored
because the SRAM cannot perform the last word write to the
array without conflicting with the read. The data stays in this
register until the next write cycle occurs. On the first write cycle
after the read(s), the stored data from the earlier write is written
into the SRAM array. This is called a posted write.
are stored in registers. The write information must be stored
because the SRAM cannot perform the last word write to the
array without conflicting with the read. The data stays in this
register until the next write cycle occurs. On the first write cycle
after the read(s), the stored data from the earlier write is written
into the SRAM array. This is called a posted write.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
on the SRAM and V
SS
to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175
Ω and 350Ω
,
with V
DDQ
= 1.5V. The
output impedance is adjusted every 1024 cycles at power up to
account for drifts in supply voltage and temperature.
account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock of the DDR-II. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in
on high-speed systems. Two echo clocks are generated by the
DDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock of the DDR-II. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in