Cypress CY7C1563V18 Manual De Usuario
Document Number: 001-05384 Rev. *F
Revised March 6, 2008
Page 28 of 28
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
are the trademarks of their respective holders.
CY7C1561V18, CY7C1576V18
CY7C1563V18, CY7C1565V18
CY7C1563V18, CY7C1565V18
© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Document Title: CY7C1561V18/CY7C1576V18/CY7C1563V18/CY7C1565V18, 72-Mbit QDR™-II+ SRAM 4-Word Burst Archi-
tecture (2.5 Cycle Read Latency)
Document Number: 001-05384
tecture (2.5 Cycle Read Latency)
Document Number: 001-05384
REV.
ECN NO.
ISSUE
DATE
ORIG. OF
CHANGE
CHANGE
DESCRIPTION OF CHANGE
**
402911
See ECN
VEE
New Data Sheet
*A
425251
See ECN
VEE
Updated the switching waveform
Corrected the typos in DC parameters
Updated the DLL section
Added additional notes in the AC parameter section
Updated the Power up sequence
Added additional parameters in the AC timing
Corrected the typos in DC parameters
Updated the DLL section
Added additional notes in the AC parameter section
Updated the Power up sequence
Added additional parameters in the AC timing
*B
437000
See ECN
IGS
ECN for Show on web
*C
461934
See ECN
NXR
Moved the Selection Guide table from page# 3 to page# 1.
Modified Application Diagram.
Changed t
Modified Application Diagram.
Changed t
TH
and t
TL
from 40 ns to 20 ns, changed t
TMSS
, t
TDIS
, t
CS
, t
TMSH
, t
TDIH
, t
CH
from
10 ns to 5 ns and changed t
TDOV
from 20 ns to 10 ns in TAP AC Switching
Characteristics table
Modified Power Up waveform.
Included Maximum ratings for Supply Voltage on V
Modified Power Up waveform.
Included Maximum ratings for Supply Voltage on V
DDQ
Relative to GND.
Changed the Maximum Ratings for DC Input Voltage from V
DDQ
to V
DD
.
Changed the Pin Definition of I
X
from Input Load current to Input Leakage current on
page#18.
*D
497567
See ECN
NXR
Changed the V
DDQ
operating voltage to 1.4V to V
DD
in the Features section, in
Operating Range table and in the DC Electrical Characteristics table
Added foot note in page# 1
Changed the Maximum rating of Ambient Temperature with Power Applied from –10°C
to +85°C to –55°C to +125°C
Changed V
Added foot note in page# 1
Changed the Maximum rating of Ambient Temperature with Power Applied from –10°C
to +85°C to –55°C to +125°C
Changed V
REF
(Max) spec from 0.85V to 0.95V in the DC Electrical Characteristics
table and in the note below the table
Updated footnote #21 to specify Overshoot and Undershoot Spec
Updated I
Updated footnote #21 to specify Overshoot and Undershoot Spec
Updated I
DD
and I
SB
values
Updated
Θ
JA
and
Θ
JC
values
Removed x9 part and its related information
Updated footnote #25
Updated footnote #25
*E
1351243
See ECN
VKN/FSU
Converted from preliminary to final
Added x8 and x9 parts
Changed t
Added x8 and x9 parts
Changed t
CYC
max spec to 8.4 ns for all speed bins
Updated footnote# 23
Updated Ordering Information table
Updated Ordering Information table
*F
2181046
See ECN VKN/AESA Added footnote# 22 related to I
DD