Aeneon 4096MB DDR2 667MHz Fully Buffered AET961FB00-30D Hoja De Datos
Los códigos de productos
AET961FB00-30D
AENEON™ Data Sheet
3
Revision 1.10, 2008-05
A Qimonda AG Brand
Doc. # 12272007-OKYD-PLKJ
DDR2 Fully Buffered
Memory Module
Operating conditions
This chapter describes the operating conditions.
TABLE 3
DC Operating Conditions
TABLE 4
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit Notes
Min.
Nom.
Max.
AMB Supply Voltage DC
V
CC
1.455
1.5
1.575
V
1)
1) At 0KHz - 30KHz
AMB Supply Voltage DC + AC
1.425
1.5
1.590
V
2)
2) AT 30KHz - 1 MHz
DRAM Supply Voltage
V
DD
1.7
1.8
1.9
V
–
Termination Voltage
V
TT
0.48 ×V
DD
0.50 ×V
DD
0.52 ×V
DD
V
–
EEPROM Supply Voltage
V
DDSPD
3.0
3.3
3.6
V
–
DC Input Logic High(SPD)
V
IH(DC)
2.1
—
V
DDSPD
V
3)
3) Applies for SMB and SPD Bus Signals
DC Input Logic Low(SPD)
V
IL(DC)
—
—
0.8
V
DC Input Logic High(RESET)
V
IH(DC)
1.0
—
—
V
4)
4) Applies for AMB CMOS Signal RESET
DC Input Logic Low(RESET)
V
IL(DC)
—
—
+0.5
V
Leakage Current (RESET)
I
L
–90
—
+90
μΑ
Leakage Current (Link)
I
L
–5
—
+5
μΑ
5)
5) For all other AMB related DC parameters, contact AENEON technical staff.
Parameter
Symbol
Rating
Unit
Notes
Min.
Max.
Voltage on any SMbus interface signal pin relative to
V
SS
V
IN
,
V
OUT
–0.5
+4.00
V
1)
Voltage on
V
DD
pin relative to
V
SS
V
DD
–0.5
+2.4
V
2)
Voltage on
V
CC
pin relative to
V
SS
V
CC
–0,3
+1.75
V
–