Renesas R5S72625 Manual De Usuario
Section 26 USB 2.0 Host/Function Module
Page 1512 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(b) FIFO Buffer Clearing
Table 26.20 shows the clearing of the FIFO buffer memory by this module. The buffer memory
can be cleared using the three bits indicated below.
can be cleared using the three bits indicated below.
Table 26.20 List of Buffer Clearing Methods
Bit Name
BCLR
DCLRM
ACLRM
Register CFIFOCTR
DnFIFOCTR
DnFIFOSEL
PIPEnCTR
Function
Clears the buffer memory
on the CPU side
on the CPU side
In this mode, after the data
of the specified pipe has
been read, the buffer
memory is cleared
automatically.
of the specified pipe has
been read, the buffer
memory is cleared
automatically.
This is the auto buffer clear
mode, in which all of the
received packets are
discarded.
mode, in which all of the
received packets are
discarded.
Clearing
method
method
Cleared by writing 1
1: Mode valid
0: Mode invalid
1: Mode valid
0: Mode invalid
(c) Buffer Areas
Table 26.21 shows the FIFO buffer memory map of this controller. The buffer memory has special
fixed areas to which pipes are assigned in advance, and user areas that can be set by the user.
fixed areas to which pipes are assigned in advance, and user areas that can be set by the user.
The buffer for the DCP is a special fixed area that is used both for control read transfers and
control write transfers.
control write transfers.
The PIPE6 to PIPE9 area is assigned in advance, but the area for pipes that are not being used can
be assigned to PIPE1 to PIPE5 as a user area.
be assigned to PIPE1 to PIPE5 as a user area.
The settings should ensure that the various pipes do not overlap. Note that each area is twice as
large as the setting value in the double buffer.
large as the setting value in the double buffer.
Also, the buffer size should not be specified using a value that is less than the maximum packet
size.
size.