Renesas R5S72625 Manual De Usuario
Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00
Page 243 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.
30 to 28
IWW[2:0]
011
R/W
Idle Cycles between Write-Read Cycles and Write-
Write Cycles
Write Cycles
These bits specify the number of idle cycles to be
inserted after the access to a memory that is
connected to the space. The target access cycles are
the write-read cycle and write-write cycle.
inserted after the access to a memory that is
connected to the space. The target access cycles are
the write-read cycle and write-write cycle.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
27 to 25
IWRWD[2:0] 011
R/W
Idle Cycles for Another Space Read-Write
Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
space. The target access cycle is a read-write one in
which continuous access cycles switch between
different spaces.
the access to a memory that is connected to the
space. The target access cycle is a read-write one in
which continuous access cycles switch between
different spaces.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted