Renesas R5S72623 Manual De Usuario
Section 23 CD-ROM Decoder
Page 1214 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
1 LINK_
SDET
0
R
Indicates that a link block was detected within seven
sectors after the start of decoding.
sectors after the start of decoding.
0 LINK_
OUT1
0
R
Indicates that the sector after ECC correction has been
identified as a run-out 1 sector.
identified as a run-out 1 sector.
This bit is only valid when an IERR interrupt is not
generated (i.e. when ECC correction was successful).
generated (i.e. when ECC correction was successful).
23.3.13
ECC/EDC Error Status Register (CROMST6)
The ECC/EDC error status register (CROMST6) indicates ECC processing error or EDC check
error before/after ECC correction.
error before/after ECC correction.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
ST_
ERR
-
ST_
ECCABT
ST_
ECCNG
ST_
ECCP
ST_
ECCQ
ST_
EDC1
ST_
EDC2
Bit Bit
Name
Initial
Value
Value
R/W Description
7
ST_ERR
0
R
Indicates that the decoded block after ECC correction
contains any error (even in a single byte).
6
0 R
Reserved
This bit is always read as 0 and cannot be modified.
5 ST_
ECCABT
0
R
Indicates that ECC processing was discontinued.
This bit is set to 1 when a transition from sector to
sector occurs while ECC correction is in progress. This
does not indicate a problem for ECC correction if the
BUF_NG bit in the CBUFST2 register is 0 at the same
time. Whether or not this is so depends on the timing of
the sector transition.
sector occurs while ECC correction is in progress. This
does not indicate a problem for ECC correction if the
BUF_NG bit in the CBUFST2 register is 0 at the same
time. Whether or not this is so depends on the timing of
the sector transition.