Renesas R5S72623 Manual De Usuario

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Section 32   General Purpose I/O Ports 
Page 1756 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
32.2.30
  Port J Control Register 0 to 2 (PJCR0 to PJCR2) 
PJCR2 to PJCR0 are 16-bit readable/writable registers that are used to select the functions of the 
multiplexed pins on port J. 
(1)  Port J Control Register 2 (PJCR2: Available Only in the SH7264 Group) 
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R/W
R/W
R
R
R/W
R/W
R
R
R/W
R/W
R
R
R/W
R/W
-
-
-
PJ10MD[1:0]
PJ9MD[1:0]
PJ8MD[1:0]
PJ11MD[1:0]
-
-
-
-
-
Bit:
Initial value:
R/W:
 
 
Bit 
Bit Name 
Initial Value
R/W 
Description 
15, 14 
 All 
Reserved 
These bits are always read as 0. The write 
value should always be 0. 
13, 12 
PJ11MD[1:0]  00 
R/W 
PJ11 Mode 
Select the function of the PJ11. 
00: PJ11 
01: PWM2H 
10: DACK1 
11: Setting prohibited 
11, 10 
 All 
Reserved 
These bits are always read as 0. The write 
value should always be 0. 
9, 8 
PJ10MD[1:0]  00 
R/W 
PJ10 Mode 
Select the function of the PJ10. 
00: PJ10 
01: PWM2G 
10: DREQ1 
11: Setting prohibited 
7, 6 
 All 
Reserved 
These bits are always read as 0. The write 
value should always be 0. 
5, 4 
PJ9MD[1:0] 
00 
R/W 
PJ9 Mode 
Select the function of the PJ9. 
00: PJ9 
01: PWM2F 
10: TEND1 
11: AUDIO_XOUT  
(640-Kbyte version only) 
3, 2 
 All 
Reserved 
These bits are always read as 0. The write 
value should always be 0.