Renesas R5S72623 Manual De Usuario
Section 8 Cache
Page 224 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
8.4
Memory-Mapped Cache
To allow software management of the cache, cache contents can be read and written by means of
MOV instructions. The instruction cache address array is mapped onto addresses H'F0000000 to
H'F07FFFFF, and the data array onto addresses H'F1000000 to H'F17FFFFF. The operand cache
address array is mapped onto addresses H'F0800000 to H'F0FFFFFF, and the data array onto
addresses H'F1800000 to H'F1FFFFFF. Only longword can be used as the access size for the
address array and data array, and instruction fetches cannot be performed.
MOV instructions. The instruction cache address array is mapped onto addresses H'F0000000 to
H'F07FFFFF, and the data array onto addresses H'F1000000 to H'F17FFFFF. The operand cache
address array is mapped onto addresses H'F0800000 to H'F0FFFFFF, and the data array onto
addresses H'F1800000 to H'F1FFFFFF. Only longword can be used as the access size for the
address array and data array, and instruction fetches cannot be performed.
8.4.1
Address Array
To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field
(for write accesses) must be specified.
(for write accesses) must be specified.
In the address field, specify the entry address for selecting the entry, the W bit for selecting the
way, and the A bit for specifying the existence of associative operation. In the W bit, B'00 is way
0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the address array is
fixed at longword, specify B'00 for bits 1 and 0 of the address.
way, and the A bit for specifying the existence of associative operation. In the W bit, B'00 is way
0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the address array is
fixed at longword, specify B'00 for bits 1 and 0 of the address.
The tag address, LRU bits, U bit (only for operand cache), and V bit are specified as data. Always
specify 0 for the upper three bits (bits 31 to 29) of the tag address.
specify 0 for the upper three bits (bits 31 to 29) of the tag address.
For the address and data formats, see figure 8.4.
The following three operations are possible for the address array.
(1) Address Array Read
The tag address, LRU bits, U bit (only for operand cache), and V bit are read from the entry
address specified by the address and the entry corresponding to the way. For the read operation,
associative operation is not performed regardless of whether the associative bit (A bit) specified
by the address is 1 or 0.
address specified by the address and the entry corresponding to the way. For the read operation,
associative operation is not performed regardless of whether the associative bit (A bit) specified
by the address is 1 or 0.
(2) Address-Array Write (Non-Associative Operation)
When the associative bit (A bit) in the address field is cleared to 0, write the tag address, LRU
bits, U bit (only for operand cache), and V bit, specified by the data field, to the entry address
specified by the address and the entry corresponding to the way. When writing to a cache line for
which the U bit = 1 and the V bit =1 in the operand cache address array, write the contents of the
cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the
data field. When 0 is written to the V bit, 0 must also be written to the U bit of that entry. Write-
bits, U bit (only for operand cache), and V bit, specified by the data field, to the entry address
specified by the address and the entry corresponding to the way. When writing to a cache line for
which the U bit = 1 and the V bit =1 in the operand cache address array, write the contents of the
cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the
data field. When 0 is written to the V bit, 0 must also be written to the U bit of that entry. Write-