Renesas R5S72623 Manual De Usuario
Section 11 Multi-Function Timer Pulse Unit 2
Page 480 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
11.3.9
Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and
TADCORB_4)
TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count
reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request
will be issued.
reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request
will be issued.
TADCORA_4 and TADCORB_4 are initialized to H'FFFF.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
11.3.10
Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4
and TADCOBRB_4)
TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or
trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and
TADCORB_4, respectively.
trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and
TADCORB_4, respectively.
TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.