Renesas R5S72623 Manual De Usuario

Section 11 Multi-Function Timer Pulse Unit 2

R01UH0134EJ0400 Rev. 4.00

Page 519 of 2108

Sep 24, 2014

SH7262 Group, SH7264 Group

TCNT_0 value

H'0000

TGRA_0

Time

TIOCA

TGRC_0

H'0520

H'0450

H'0200

H'0520

H'0450

H'0200

TGRB_0

TGRA_0

Transfer

Figure 11.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for

TGRC_0 to TGRA_0 Transfer Timing

11.4.4

Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.

This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.

Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.

Table 11.42 shows the register combinations used in cascaded operation.

Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the

counters operates independently in phase counting mode.

Table 11.42 Cascaded Combinations

Combination Upper

Bits

Lower 16 Bits

Channels 1 and 2

TCNT_1

TCNT_2

For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional
input capture input pins can be specified by the input capture control register (TICCR). The edge
detection that is the condition for input capture uses a signal representing the logical OR of the
original input pin and the added input pins. For details, see (4) Cascaded Operation Example (c).