Renesas R5S72623 Manual De Usuario
Section 11 Multi-Function Timer Pulse Unit 2
Page 608 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
11.7.13
Counter Value during Complementary PWM Mode Stop
When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM
mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000.
mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000.
When restarting complementary PWM mode, counting begins automatically from the initialized
state. This explanatory diagram is shown in figure 11.108.
state. This explanatory diagram is shown in figure 11.108.
When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to
the initial values.
the initial values.
TGRA_3
TCDR
TDDR
H'0000
TCNT_3
TCNT_4
Complementary PWM
mode operation
Complementary PWM
mode operation
mode operation
Counter
operation stop
operation stop
Complementary
PMW restart
PMW restart
Figure 11.108 Counter Value during Complementary PWM Mode Stop
11.7.14
Buffer Operation Setting in Complementary PWM Mode
In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting
register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3,
TGRA_4, and TGRB_4).
register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3,
TGRA_4, and TGRB_4).
In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit
settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a
buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for
TGRA_4, and TCBR functions as the TCDR's buffer register.
settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a
buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for
TGRA_4, and TCBR functions as the TCDR's buffer register.