Renesas R5S72623 Manual De Usuario

 

 

 

 

 

 

Section 12   Compare Match Timer 

 

Page 656 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

 
SH7262 Group, SH7264 Group 

This module has channels and each of them to which a different vector address is allocated has a 
compare match interrupt. When both the compare match flag (CMF) and the interrupt enable bit 
(CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to 
activate a CPU interrupt, the priority of channels can be changed by the interrupt controller 
settings. For details, see section 7, Interrupt Controller. 

Clear the CMF bit to 0 by the user exception handling routine. If this operation is not carried out, 
another interrupt will be generated. By setting the interrupt controller, the direct memory access 
controller can be activated when a compare match interrupt is requested. In this case, an interrupt 
is not issued to the CPU. If the setting to activate the direct memory access controller has not been 
made, an interrupt request is sent to the CPU. The CMF bit is automatically cleared to 0 when data 
is transferred by the direct memory access controller. 

When CMCOR and CMCNT match, a compare match signal is generated at the last state in which 
the values match (the timing when the CMCNT value is updated to H'0000) and the CMF bit in 
CMCSR is set to 1. That is, after a match between CMCOR and CMCNT, the compare match 
signal is not generated until the next CMCNT counter clock input. Figure 12.4 shows the timing of 
CMF bit setting.