Renesas R5S72623 Manual De Usuario
Section 13 Watchdog Timer
R01UH0134EJ0400 Rev. 4.00
Page 663 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
13.3
Register Descriptions
Table 13.2 shows the register configuration.
Table 13.2 Register Configuration
Register Name
Abbreviation R/W
Initial
Value Address
Value Address
Access
Size
Size
Watchdog timer counter
WTCNT R/W
H'00 H'FFFE0002
16*
Watchdog timer control/status
register
register
WTCSR R/W
H'18 H'FFFE0000
16*
Watchdog reset control/status
register
register
WRCSR R/W
H'1F H'FFFE0004
16*
Note: * For the access size, see section 13.3.4, Notes on Register Access.
13.3.1
Watchdog Timer Counter (WTCNT)
WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock
signal. When an overflow occurs, it generates a watchdog timer overflow signal (
signal. When an overflow occurs, it generates a watchdog timer overflow signal (
WDTOVF) in
watchdog timer mode and an interrupt in interval timer mode.
Use word access to write to WTCNT, writing H'5A in the upper byte. Use byte access to read
from WTCNT.
from WTCNT.
Note: The method for writing to WTCNT differs from that for other registers to prevent
erroneous writes. See section 13.3.4, Notes on Register Access, for details.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W: