Renesas R5S72623 Manual De Usuario

 

 

Section 15   Serial Communication Interface with FIFO 

 

 

Page 740 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

3 

MCE 

0 

R/W 

Modem Control Enable 

Enables modem control signals 

CTS and RTS. 

The MCE bit should always be 0 for channels 0 and 2 to 7 
on the SH7262, for channels 0, 2, and 4 to 7 on the 
SH7264, and in clock synchronous mode. 

0: Modem signal disabled* 

1: Modem signal enabled 

Note:  * 

CTS is fixed at active 0 regardless of the input 
value, and 

RTS is also fixed at 0.  

2 

TFRST 

0 

R/W 

Transmit FIFO Data Register Reset 

Disables the transmit data in the transmit FIFO data 
register and resets the data to the empty state. 

0: Reset operation disabled* 

1: Reset operation enabled 

Note:  *  Reset operation is executed by a power-on 

reset.  

1 

RFRST 

0 

R/W 

Receive FIFO Data Register Reset 

Disables the receive data in the receive FIFO data 
register and resets the data to the empty state. 

0: Reset operation disabled* 

1: Reset operation enabled 

Note:  *  Reset operation is executed by a power-on 

reset.  

0 LOOP 

0 

R/W 

Loop-Back 

Test 

Internally connects the transmit output pin (TxD) and 
receive input pin (RxD) and internally connects the 

RTS 

pin and 

CTS pin and enables loop-back testing. 

0: Loop back test disabled 

1: Loop back test enabled