Renesas R5S72623 Manual De Usuario
Section 17 I
2
C Bus Interface 3
R01UH0134EJ0400 Rev. 4.00
Page 881 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
17.4.7
Noise Filter
The logic levels at the SCL and SDA pins are routed through noise filters before being latched
internally. Figure 17.17 shows a block diagram of the noise filter circuit.
internally. Figure 17.17 shows a block diagram of the noise filter circuit.
The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed
forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this
signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do
not agree, the previous value is held.
signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed
forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this
signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do
not agree, the previous value is held.
C
Q
D
C
Q
D
C
Q
1
0
D
NF2CYC
SCL or SDA
input signal
input signal
Internal
SCL or SDA
signal
SCL or SDA
signal
Sampling clock
Sampling
clock
clock
Peripheral clock
cycle
Latch
Latch
Match
detector
Latch
Match
detector
Figure 17.17 Block Diagram of Noise Filter