Renesas R5S72622 Manual De Usuario
Section 26 USB 2.0 Host/Function Module
Page 1510 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Buffer Memory
PIPEBUF registers
BUFNMB = 0, BUFSIZE = 3
BUFNMB = 4, BUFSIZE = 0
BUFNMB = 5, BUFSIZE = 0
BUFNMB = 6, BUFSIZE = 3
BUFNMB = 10, BUFSIZE = 7
BUFNMB = 18, BUFSIZE = 3
BUFNMB = 22, BUFSIZE = 7
BUFNMB = 28, BUFSIZE = 2
PIPE0
PIPE6
PIPE7
PIPE5
PIPE1
PIPE2
PIPE3
PIPE4
CURPIPE = 1
CURPIPE = 3
CURPIPE = 6
FIFO Port
CFIFO Port
D0FIFO Port
D1FIFO Port
Notes: When pipe 8 and pipe 9 are not in use, BUFSIZE and such are not set.
Figure 26.9 Example of a Buffer Memory Map
(a) Buffer Status
Tables 26.18 and 26.19 show the buffer status. The buffer memory status can be confirmed using
the BSTS bit in DCPCTR and the INBUFM bit in PIPEnCTR. The access direction for the buffer
memory can be specified using either the DIR bit in PIPECFG or the ISEL bit in CFIFOSEL
(when DCP is selected).
the BSTS bit in DCPCTR and the INBUFM bit in PIPEnCTR. The access direction for the buffer
memory can be specified using either the DIR bit in PIPECFG or the ISEL bit in CFIFOSEL
(when DCP is selected).
The INBUFM bit is valid for PIPE0 to PIPE5 in the sending direction.
For an IN pipe uses double buffer, the BSTS bit can be used to monitor the buffer memory status
of CPU side and the INBUFM bit to monitor the buffer memory status of SIE side. In the case like
the BEMP interrupt may not shows the buffer empty status because the CPU (direct memory
access controller) writes data slowly, the INBUFM bit can be used to confirm the end of sending.
of CPU side and the INBUFM bit to monitor the buffer memory status of SIE side. In the case like
the BEMP interrupt may not shows the buffer empty status because the CPU (direct memory
access controller) writes data slowly, the INBUFM bit can be used to confirm the end of sending.