Renesas R5S72622 Manual De Usuario

 

 

Section 11   Multi-Function Timer Pulse Unit 2 
 

Page 540 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

3 

TCNT_3 

Start of up-count from value set 
in dead time register 

Maskable by TRWER 
setting* 

 

TGRA_3 

Set TCNT_3 upper limit value  
(1/2 carrier cycle + dead time) 

Maskable by TRWER 
setting* 

 

TGRB_3 

PWM output 1 compare register 

Maskable by TRWER 
setting* 

 

TGRC_3 

TGRA_3 buffer register 

Always readable/writable 

 

TGRD_3 

PWM output 1/TGRB_3 buffer 
register 

Always readable/writable 

4 

TCNT_4 

Up-count start, initialized to 
H'0000 

Maskable by TRWER 
setting* 

 

TGRA_4 

PWM output 2 compare register 

Maskable by TRWER 
setting* 

 

TGRB_4 

PWM output 3 compare register 

Maskable by TRWER 
setting* 

 

TGRC_4 

PWM output 2/TGRA_4 buffer 
register 

Always readable/writable 

 

TGRD_4 

PWM output 3/TGRB_4 buffer 
register 

Always readable/writable 

Timer dead time data register 
(TDDR) 

Set TCNT_4 and TCNT_3 offset 
value (dead time value) 

Maskable by TRWER 
setting* 

Timer cycle data register  
(TCDR) 

Set TCNT_4 upper limit value  
(1/2 carrier cycle) 

Maskable by TRWER 
setting* 

Timer cycle buffer register  
(TCBR) 

TCDR buffer register 

Always readable/writable 

Subcounter (TCNTS) 

Subcounter for dead time 
generation 

Read-only 

Temporary register 1 (TEMP1) 

PWM output 1/TGRB_3 
temporary register 

Not readable/writable 

Temporary register 2 (TEMP2) 

PWM output 2/TGRA_4 
temporary register 

Not readable/writable 

Temporary register 3 (TEMP3) 

PWM output 3/TGRB_4 
temporary register 

Not readable/writable 

Note:  *  Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER 

(timer read/write enable register).