Renesas R5S72624 Manual De Usuario

 

Section 19   Serial I/O with FIFO 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 965 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

The SIOFTxD transmit timing and SIOFRxD receive timing relative to the SIOFSCK can be set as 
the sampling timing in the following ways. The transmit/receive timing is set using the REDG bit 
in SIMDR. 

  Falling-edge sampling 
  Rising-edge sampling (possible only in master mode) 
 
Figure 19.4 shows the transmit/receive timing. 

SIOFSCK

SIOFSYNC

SIOFTxD

SIOFRxD

SIOFSCK

SIOFSYNC

SIOFTxD

SIOFRxD

(a) Falling-edge sampling 

(a) Rising-edge sampling 

Receive timing
Transmit timing

Receive timing
Transmit timing

 

This module performs the following transfer. 

  Transmit/receive data: Transfer of 8-bit monaural/16-bit monaural/16-bit stereo data 
 
(1)  Transfer Mode 

 This module supports the following two transfer modes as listed in table 19.4. The transfer mode 
can be specified by the TRMD1 and TRMD0 bits in SIMDR. 

Table 19.4  Serial Transfer Modes 

Slave mode 

Synchronous pulse 

SYNCDL bit 

Master mode