Renesas R5S72624 Manual De Usuario
Section 23 CD-ROM Decoder
Page 1202 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
2, 1
All
0
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
0
1 R/W
Reserved
This bit is always read as 1. The write value should
always be 1.
always be 1.
Table 23.2 Register Settings for Sync Code Maintenance Function
SY_AUT SY_IEN SY_DEN Operating
Mode
1
Automatic
sync
maintenance mode
0 0 1 External
sync
mode
0 1 0 Interpolated
sync
mode
0 1 1 Interpolated
sync
plus
external sync mode
0 0 0 Setting
prohibited
23.3.3
Decoding Mode Control Register (CROMCTL0)
The decoding mode control register (CROMCTL0) enables/disables the various functions, selects
criteria for mode or form determination, and specifies the sector type. The setting of this register
becomes valid at the sector-to-sector transition
criteria for mode or form determination, and specifies the sector type. The setting of this register
becomes valid at the sector-to-sector transition
7
6
5
4
3
2
1
0
1
0
0
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
MD_
DESC
-
MD_
AUTO
MD_
AUTOS1
MD_
AUTOS2
MD_SEC[2:0]
Bit Bit
Name
Initial
Value
Value
R/W Description
7
MD_DESC 1
R/W
Descrambling Function ON/OFF
0: Disables descrambling function
1: Enables descrambling function