Renesas R5S72621 Manual De Usuario
Section 22 Renesas SPDIF Interface
R01UH0134EJ0400 Rev. 4.00
Page 1169 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
22.7.7
Transmitter Channel 1 Status Register (TLCS)
The 30-bit register stores the channel status information to be transmitted. For each channel,
channel status information per frame consists of 192 bits. Because necessary data covers only the
30 bits that are set in the following register, zeros continue to be sent after the transmission of the
first 30 bits.
channel status information per frame consists of 192 bits. Because necessary data covers only the
30 bits that are set in the following register, zeros continue to be sent after the transmission of the
first 30 bits.
31
30
29
28
27
26
25
24
-
-
0
0
0
-
-
CLAC[1:0]
0
0
0
W
W
W
W
W
W
W
W
CHNO[3:0]
FS[3:0]
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
SRCNO[3:0]
15
14
13
12
11
10
9
8
0
0
0
0
0
CATCD[7:0]
0
0
0
W
W
W
W
W
W
W
W
7
6
5
4
3
2
1
0
0
0
0
0
0
-
-
CTL[4:0]
0
0
0
W
W
W
W
W
W
W
W
-
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
Value
Value
R/W Description
31, 30
W
Reserved
29, 28
CLAC[1:0]
All 0
W
Clock Accuracy
00: Level 2
01: Level 1
10: Level 3
11: Reserved
27 to 24 FS[3:0]
All 0
W
Sample Frequency (FS)
0000: 44.1 kHz
0010: 48 kHz
0011: 32 kHz