Renesas R5S72621 Manual De Usuario
Section 2 CPU
Page 84 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
2.4.6
Branch Instructions
Table 2.15 Branch Instructions
Instruction
Instruction Code
Operation
Execu-
tion
Cycles
T Bit
Compatibility
SH2,
SH2E SH4 SH-2A
BF label
10001011dddddddd When T = 0, disp 2 + PC
PC,
When T = 1, nop
3/1*
Yes Yes Yes
BF/S label
10001111dddddddd Delayed branch
When T = 0, disp
2 + PC
PC,
When T = 1, nop
2/1*
Yes Yes Yes
BT label
10001001dddddddd When T = 1, disp 2 + PC
PC,
When T = 0, nop
3/1*
Yes Yes Yes
BT/S label
10001101dddddddd Delayed branch
When T = 1, disp
2 + PC
PC,
When T = 0, nop
2/1*
Yes Yes Yes
BRA label
1010dddddddddddd Delayed branch,
disp
2 + PC PC
2
Yes Yes Yes
BRAF Rm
0000mmmm00100011 Delayed branch,
Rm + PC
PC
2
Yes Yes Yes
BSR label
1011dddddddddddd Delayed branch, PC PR,
disp
2 + PC PC
2
Yes Yes Yes
BSRF Rm
0000mmmm00000011 Delayed branch, PC PR,
Rm + PC
PC
2
Yes Yes Yes
JMP @Rm
0100mmmm00101011 Delayed branch, Rm PC
2
Yes Yes Yes
JSR @Rm
0100mmmm00001011 Delayed branch, PC PR,
Rm
PC
2
Yes Yes Yes
JSR/N @Rm
0100mmmm01001011 PC-2 PR, Rm PC
3
Yes
JSR/N @@(disp8,TBR)
10000011dddddddd PC-2 PR,
(disp
4 + TBR) PC
5
Yes
RTS
0000000000001011 Delayed branch, PR PC
2
Yes Yes Yes
RTS/N
0000000001101011 PR PC
3
Yes
RTV/N Rm
0000mmmm01111011 Rm R0, PR PC
3
Yes
Note: * One cycle when the program does not branch.