Renesas R5S72621 Manual De Usuario
Section 23 CD-ROM Decoder
Page 1204 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
2 to 0
MD_SEC
[2:0]
[2:0]
010 R/W
Sector
Type
000: Setting prohibited
001: Mode 0
010: Mode 1
011: Long (Mode 0, Mode 1, or Mode 2 with no
EDC/ECC data)
100: Setting prohibited
101: Mode 2 Form 1
110: Mode 2 Form 2
111: Mode 2 with automatic form detection
If the form cannot be determined when set to B'111, it is
processed as Mode 2 not XA.
processed as Mode 2 not XA.
23.3.4
EDC/ECC Check Control Register (CROMCTL1)
The EDC/ECC check control register (CROMCTL1) controls EDC/ECC checking. The setting of
this register becomes valid at the sector-to-sector transition
this register becomes valid at the sector-to-sector transition
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
M2F2
EDC
MD_DEC[2:0]
MD_PQREP[1:0]
-
-
Bit Bit
Name
Initial
Value
Value
R/W Description
7
M2F2EDC 1
R/W
For Mode 2 Form 2, disables the EDC function for
sectors where all bits of the EDC are 0.
When this bit set to 1 and all bits of the EDC for a Mode
2 Form 2 sector are 0, an IERR interrupt is not
generated even if the result of EDC checking is ‘fail’.
generated even if the result of EDC checking is ‘fail’.