Renesas R5S72621 Manual De Usuario
Section 27 Video Display Controller 3
Page 1588 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
27.7.11
Video Line Offset Register (VIDEO_LINE_OFFSET)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VIDEO_LINE_OFFSET[15:0]
VIDEO_LINE_OFFSET[31:16]
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 0
VIDEO_LINE_
OFFSET[31:0]
OFFSET[31:0]
H'00000000 R/W
These bits specify the line offset. According to the
BURST_MODE_MAIN bit setting in the
VIDEO_MODE register, the lower bits should be
set as follows.
BURST_MODE_MAIN bit setting in the
VIDEO_MODE register, the lower bits should be
set as follows.
In 16-byte burst transfer: The lower four bits should
always be 0000.
always be 0000.
In 128-byte burst transfer: The lower seven bits
should always be 000_0000.
should always be 000_0000.