Renesas R5S72621 Manual De Usuario
Section 27 Video Display Controller 3
Page 1598 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
27.7.18
Graphics Block Interrupt Control Registers (GRCINTCNT1 and GRCINTCNT2)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W*
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INT_
UF_EN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNDER_
FLOW
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 17
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
16 INT_UF_EN
0
R/W
Enables
output of underflow interrupts.
0: Disabled
1: Enabled
15 to 1
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
0 UNDER_
FLOW
0 R/W*
2
Indicates the underflow status of the buffer used to
read graphics images from the memory.*
read graphics images from the memory.*
1
0: No underflow has occurred.
1: An underflow has occurred.
Notes: 1. The status bit (bit 0) always operates regardless of the operation enabling bit settings.
After being set to 1, the status bit remains at 1 until cleared 0.
2. Only 0 can be written.