Renesas R5S72621 Manual De Usuario
Section 28 Sampling Rate Converter
R01UH0134EJ0400 Rev. 4.00
Page 1647 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
28.2.5
Control Register (SRCCTRL)
SRCCTRL is a 16-bit readable/writable register that enables/disables the module operation,
enables/disables the interrupt requests, and specifies flush processing, clear processing of the
internal work memory, and the input and output sampling rates.
enables/disables the interrupt requests, and specifies flush processing, clear processing of the
internal work memory, and the input and output sampling rates.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
⎯
⎯
CEEN SRCEN UDEN
OVEN
FL
CL
IFS[3:0]
⎯
⎯
⎯
OFS
Bit Bit
Name
Initial
Value
Value
R/W Description
15, 14
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
13
CEEN
0
R/W
Conversion End Interrupt Enable
Enables/disables the conversion end interrupt to be
generated when the CEF bit in SRCSTAT is set to 1
after flush processing is completed and all the output
data is read.
generated when the CEF bit in SRCSTAT is set to 1
after flush processing is completed and all the output
data is read.
0: Disables conversion end interrupt requests.
1: Enables conversion end interrupt requests.
12 SRCEN
0 R/W
Module
Enable
Enables/disables this module operation. Writing 1
while SRCEN
while SRCEN
0 clears the internal work memory.
0: Disables this module operation.
1: Enables this module operation.
Note: When SRCEN
1, do not change the settings
of the following bits.
Register Bit Bit
Name
SRCIDCTRL 9
IED
SRCODCTRL
10, 9
OCH, OED
SRCCTRL
7 to 4, 0
IFS[3:0], OFS