Renesas R5S72621 Manual De Usuario
Section 6 Exception Handling
Page 134 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(2) Exception Handling Triggered by Address Errors, Register Bank Errors, Interrupts,
and Instructions
SR and PC are saved to the stack indicated by R15. In the case of interrupt exception handling
other than NMI with usage of the register banks enabled, general registers R0 to R14, control
register GBR, system registers MACH, MACL, and PR, and the vector table address offset of the
interrupt exception handling to be executed are saved to the register banks. In the case of
exception handling due to an address error, register bank error, NMI interrupt, or instruction,
saving to a register bank is not performed. When saving is performed to all register banks,
automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt
controller setting must have been made so that register bank overflow exceptions are not accepted
(the BOVE bit in IBNR of the interrupt controller is 0). If a setting to accept register bank
overflow exceptions has been made (the BOVE bit in IBNR of the interrupt controller is 1),
register bank overflow exception will be generated. In the case of interrupt exception handling, the
interrupt priority level is written to the I3 to I0 bits in SR. In the case of exception handling due to
an address error or instruction, the I3 to I0 bits are not affected. The exception service routine start
address is then fetched from the exception handling vector table and the program begins running
from that address.
other than NMI with usage of the register banks enabled, general registers R0 to R14, control
register GBR, system registers MACH, MACL, and PR, and the vector table address offset of the
interrupt exception handling to be executed are saved to the register banks. In the case of
exception handling due to an address error, register bank error, NMI interrupt, or instruction,
saving to a register bank is not performed. When saving is performed to all register banks,
automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt
controller setting must have been made so that register bank overflow exceptions are not accepted
(the BOVE bit in IBNR of the interrupt controller is 0). If a setting to accept register bank
overflow exceptions has been made (the BOVE bit in IBNR of the interrupt controller is 1),
register bank overflow exception will be generated. In the case of interrupt exception handling, the
interrupt priority level is written to the I3 to I0 bits in SR. In the case of exception handling due to
an address error or instruction, the I3 to I0 bits are not affected. The exception service routine start
address is then fetched from the exception handling vector table and the program begins running
from that address.
6.1.3
Exception Handling Vector Table
Before exception handling begins running, the exception handling vector table must be set in
memory. The exception handling vector table stores the start addresses of exception service
routines. (The reset exception handling table holds the initial values of PC and SP.)
memory. The exception handling vector table stores the start addresses of exception service
routines. (The reset exception handling table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets, from
which the vector table addresses are calculated. During exception handling, the start addresses of
the exception service routines are fetched from the exception handling vector table, which is
indicated by this vector table address.
which the vector table addresses are calculated. During exception handling, the start addresses of
the exception service routines are fetched from the exception handling vector table, which is
indicated by this vector table address.