Renesas R5S72621 Manual De Usuario

 

Section 33   Power-Down Modes 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1791 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

7 to 4 

 All 

1 

R 

Reserved 

These bits are always read as 1. The write value 
should always be 1. 

3 

RAMWE3 

1 

R/W 

RAM Write Enable 3 (corresponding area: page 3* in 
high-speed on-chip RAM) 

0: Writing to page 3 is disabled. 

1 Writing to page 3 is enabled. 

2 

RAMWE2 

1 

R/W 

RAM Write Enable 2 (corresponding area: page 2* in 
high-speed on-chip RAM) 

0: Writing to page 2 is disabled. 

1: Writing to page 2 is enabled. 

1 

RAMWE1 

1 

R/W 

RAM Write Enable 1 (corresponding area: page 1* in 
high-speed on-chip RAM) 

0: Writing to page 1 is disabled. 

1: Writing to page 1 is enabled. 

0 

RAMWE0 

1 

R/W 

RAM Write Enable 0 (corresponding area: page 0* in 
high-speed on-chip RAM) 

0: Writing to page 0 is disabled. 

1: Writing to page 0 is enabled. 

Note:  *  For addresses in each page, see section 31, On-Chip RAM. 

 

SYSCR3 is an 8-bit readable/writable register that enables or disables access (read and write) to a 
specified page in the large-capacity on-chip RAM. 

When a VRAMEn (n = 0 to 5) bit is set to 1, access to page n is enabled. When a VRAMEn bit is 
cleared to 0, page n cannot be accessed. In this case, an undefined value is returned when reading 
data or fetching an instruction from page n, and writing to page n is ignored. The initial value of a 
VRAMEn bit is 1.  

SYSCR3 should be set with a program located in an area other than the large-capacity on-chip RAM. Furthermore, an 

instruction to read SYSCR3 should be located immediately after the instruction to write to SYSCR3. If not, normal access 

is not guaranteed. 

Note:  When writing to this register, see section 33.4, Usage Notes.