Renesas R5S72621 Manual De Usuario
Section 37 Electrical Characteristics
R01UH0134EJ0400 Rev. 4.00
Page 2023 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
37.4.9
I
2
C Bus Interface 3 Timing
Table 37.13 (1) I
2
C Bus Interface 3 Timing I
2
C Bus Format
Item Symbol
Min.
Max.
Unit
Figure
SCL input cycle time
t
SCL
12
t
pcyc
*
1
+ 600
ns
Figure
37.52
(1)
SCL input high pulse width
t
SCLH
3
t
pcyc
*
1
+ 300
ns
SCL input low pulse width
t
SCLL
5
t
pcyc
*
1
+ 300
ns
SCL, SDA input rise time
t
Sr
300
ns
SCL, SDA input fall time
t
Sf
300
ns
SCL, SDA input spike pulse removal time*
2
t
SP
1,
2
t
pcyc
*
1
SDA input bus free time
t
BUF
5
t
pcyc
*
1
Start condition input hold time
t
STAH
3
t
pcyc
*
1
Retransmit start condition input setup time
t
STAS
3
t
pcyc
*
1
Stop condition input setup time
t
STOS
3
t
pcyc
*
1
Data input setup time
t
SDAS
1
t
pcyc
*
1
+ 20
ns
Data input hold time
t
SDAH
0
ns
SCL, SDA capacitive load
Cb
0
400
pF
SCL, SDA output fall time*
3
t
Sf
250
ns
Notes: 1. t
pcyc
indicates the peripheral clock (P
) cycle.
2. Depends on the value of NF2CYC.
3. Indicates the I/O buffer characteristic.
[Legend]
S: Start condition
P: Stop condition
Sr: Start condition for retransmission
S: Start condition
P: Stop condition
Sr: Start condition for retransmission
SCL
V
IH
V
IL
t
STAH
t
BUF
P*
S*
t
Sf
t
Sr
t
SCL
t
SDAH
t
SCLH
t
SCLL
SDA
Sr*
t
STAS
t
SP
t
STOS
t
SDAS
P*
Figure 37.52 (1) Input/Output Timing