Renesas R5S72621 Manual De Usuario
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 499 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
11.3.24
Timer Cycle Buffer Register (TCBR)
TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer
register for the TCDR register. The TCBR register values are transferred to the TCDR register
with the transfer timing set in the TMDR register. The initial value of TCBR is H'FFFF.
register for the TCDR register. The TCBR register values are transferred to the TCDR register
with the transfer timing set in the TMDR register. The initial value of TCBR is H'FFFF.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.
11.3.25
Timer Interrupt Skipping Set Register (TITCR)
TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and
specifies the interrupt skipping count. This module has one TITCR.
specifies the interrupt skipping count. This module has one TITCR.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
T3AEN
3ACOR[2:0]
T4VEN
4VCOR[2:0]
Bit Bit
Name
Initial
value R/W Description
value R/W Description
7 T3AEN 0 R/W
T3AEN
Enables or disables TGIA_3 interrupt skipping.
0: TGIA_3 interrupt skipping disabled
1: TGIA_3 interrupt skipping enabled
6 to 4
3ACOR[2:0] 000
R/W
These bits specify the TGIA_3 interrupt skipping count
within the range from 0 to 7.*
within the range from 0 to 7.*
For details, see table 11.38.
3 T4VEN 0 R/W
T4VEN
Enables or disables TCIV_4 interrupt skipping.
0: TCIV_4 interrupt skipping disabled
1: TCIV_4 interrupt skipping enabled