Renesas R5S72621 Manual De Usuario
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 603 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
11.7.8
Contention between Buffer Register Write and TCNT Clear
When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register
(TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to
TGR by the buffer operation is the data before write.
(TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to
TGR by the buffer operation is the data before write.
Figure 11.103 shows the timing in this case.
Address
Write signal
TCNT clear
signal
signal
Buffer transfer
signal
signal
TGR write cycle
T1
T2
Buffer register
address
N
N
M
Buffer register write data
Buffer register
TGR
P
φ
Figure 11.103 Contention between Buffer Register Write and TCNT Clear